| 摘要 |
PROBLEM TO BE SOLVED: To surely conduct a sampling of input signals without saturating an amplifier by providing a bypass means in parallel with a capacitor which constitutes a feedback circuit for a low pass filter in a PLL control signal generator. SOLUTION: When no binary reproducing signals RF2 are inputted to a PLL control signal generator, only a bias current Ib of an amplifier A1, which constitutes a charge pump/loop filter 5, flows to charge up a capacitor C1. When the capacitor C1 is completely charged up, a frequency control signal approaches to an operating point voltage. Thus, if a reproducing operation is restarted and the signals RF2 are inputted to the PLL control signal generator, the frequency control signal reaches with the operating point till the time where PLL pulling in synchronous signals are inputted because the voltage of the frequency control signal is close to the operating point voltage. In other words, by synchronizing the signals RF2 and a sampling clock SC, a data reading start position signal is surely detected. |
