发明名称 MOUNTING STRUCTURE OF LSI CHIP ON MULTILAYER SUBSTRATE
摘要 <p>PROBLEM TO BE SOLVED: To accelerate the high speed performance and reduce the size of an LSI chip and increase the number of terminals by removing the influence by the through hole capacitance to prevent noise. SOLUTION: This is a mounting structure of an LSI chip for mounting an LSI chip 1 on a multilayer substrate 5 made by stacking a plurality of signal layer 5a-5h through insulators 6. This mounting structure comprises the LSI chip 1 having a step-formed terminal face 2 and terminals 3 formed on each of steps 2a-2e, the mutilayer substrate 5 having an LSI chip mounting section which is step-formed from the mounting face side in conformity with the terminal face 2 of the LSI chip 1, and connections 9 which are formed on exposed parts 8a-8e of each signal layer exposed when the substrate 5 is step-formed to be connected to the terminals 3 of the LSI chip 1. When mounting the LSI chip 1, the LSI chip 1 is inserted into the LSI chip mounting section of the substrate 5 and then the connections 9 and the terminals 3 of the LSI chip 1 are connected.</p>
申请公布号 JP2000252381(A) 申请公布日期 2000.09.14
申请号 JP19990050287 申请日期 1999.02.26
申请人 NEC CORP 发明人 FUKUMA YASUAKI
分类号 H01L23/12;H01L21/60;(IPC1-7):H01L23/12 主分类号 H01L23/12
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