| 摘要 |
PROBLEM TO BE SOLVED: To prevent a logic circuit from malfunctioning irrespective of whether the time width of a noise pulse is long or short by providing a signal invalidating means, which prevents signals of voltage drops from being transmitted to the logic circuit, if a 1st and a 2nd load resistance have the pulsating voltage drops at the same time. SOLUTION: A group of NOT circuits 7, 8 and 11 and a NOR circuit 13 and a group of NOT circuits 9, 10 and 12 and a NOR circuit 14 are constituted in a right-left symmetrical relation with a high dielectric strength MOSFET 1 and a high dielectric strength MOSFET 2. The thresholds of the NOT circuits 8 and 9 are set at less than those of the NOT circuits 7 and 10. The inversion output of the NOT circuit 8 is therefore masked with the output of the NOT circuit 7 via the NOR circuit 13. Similarly, the inversion output of the NOT circuit 9 is masked with the output of the NOT circuit 10 through the NOR circuit 14. Consequently, a noise signal is prevented from being transmitted to the set input and reset input of an RS latch 15.
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