发明名称 PEAK HOLD CIRCUIT AND BOTTOM HOLD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a peak hold circuit allowing improvement of a rising/ falling time, allowing accurate control of a droop rate (a decrease rate), and capable of maintaining accuracy, with a relatively simple circuit and a small number of elements. SOLUTION: This feedback type peak hold circuit having both a capacity means C1 and an emitter follower Q5 provided in an output stage of a differential amplifier circuit to give feedback is provided with clamp circuits P4, Q4 for clamping a collector of a feedback side transistor Q2 in the differential amplifier circuit comprising npn transistors Q1, Q2 and pnp transistors P1, P2.
申请公布号 JP2000249728(A) 申请公布日期 2000.09.14
申请号 JP19990055161 申请日期 1999.03.03
申请人 SONY CORP 发明人 WAKIZAKA HIROSHI
分类号 G11C27/00;G01R19/04;(IPC1-7):G01R19/04 主分类号 G11C27/00
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