| 摘要 |
<p>The system uses a memory to retain indices and associated addresses for rapid identification of addresses. The system is intended to associate indices with addresses, selecting from a large number of available indices. It includes a memory (30) containing the indices and respective verification words corresponding to the predetermined bits of the addresses associated with the index. A compacting circuit (39) receives a current address (A) and suppresses within this address the bits determined by a pattern (41), such that the suppressed bits correspond to the verification word bits. The compacted address provided by the compacting circuit serves to select a reading position within the memory. A comparator (45) indicates that the current address corresponds to the selected memory position if the bits of the verification word are equal to the corresponding bits of the current address.</p> |
