CLOCK SIGNAL SUPPLY PATH OF SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS WIRE ARRANGING METHOD

摘要

PROBLEM TO BE SOLVED: To facilitate the design and to suppress increases in chip area and power consumption by providing a 3rd step, etc., wherein a clock buffer element is inserted and arranged and clock wiring is performed between a clock input element and the clock buffer element. SOLUTION: The delay time of each path is found from connection information on respective clock input terminals of the semiconductor integrated circuit and the arrangement or wire arrangement result of the elements to calculate a slack (S1). The permissible range of the propagation delay difference of the path is determined by the clock input elements corresponding to the slack (S2). Then information on the determined permissible range of the clock propagation delay difference is used and the clock buffer element is inserted and arranged so as to put the clock propagation delay difference in the permissible range. This method facilitates the delay and suppresses increases in chip area and power consumption.