发明名称 |
Synchronous clock generator including a false lock detector |
摘要 |
A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.
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申请公布号 |
US6119242(A) |
申请公布日期 |
2000.09.12 |
申请号 |
US19990318293 |
申请日期 |
1999.05.25 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
HARRISON, RONNIE M. |
分类号 |
G06F1/06;G06F1/10;G11C7/22;H03L7/07;H03L7/081;H03L7/087;H03L7/089;H03L7/095;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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