Output multiplexing implementation for a simultaneous operation flash memory device

摘要

A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.