| 摘要 |
An IC tester is provided which is capable of performing a high speed test of an IC under test without using a plurality of pin units for one pin of the IC under test. For each of pins of an IC under test are provided first and second two pattern generators first and second waveform shaping devices having waveform memories and respectively, first and second logical comparators and first and second failure analysis memories. Odd addresses of the first waveform memory are accessed by the first pattern generator, even addresses of the second waveform memory are accessed by the second pattern generator, and waveform data from these two waveform shaping devices are multiplexed for half of the period of a test pattern signal of the normal speed to set and reset first and scond set/reset flip-flops SRFF1 and SRFF2. As a result, a test pattern signal of high speed of twice the normal speed is produced and a test of an IC under test is implemented at high speed of twice the normal speed. |
