发明名称 |
Instruction prefetching apparatus and instruction prefetching method for processing in a processor |
摘要 |
The present invention intends to provide an instruction prefetching apparatus capable of reducing a delay caused by branch prediction error by prefetching instruction based on a condition of a conditional branch instruction if the condition is already determined at the prefetching of the branch instruction. In the apparatus, a first decoding unit judges whether or not a processed instruction is a conditional branch instruction or not and whether or not the instruction is a condition generate instruction which determines branch condition. A condition determination signal generating means compares an address of a condition generate instruction with the content of a program counter to judge whether the condition is already determined or not, and according to the judgment, outputs a condition determination signal to a condition determination judging unit. In response to the signal input, the condition determination judging unit outputs prefetch address information for generating address to a prefetch address generating unit, using a condition code.
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申请公布号 |
US6119221(A) |
申请公布日期 |
2000.09.12 |
申请号 |
US19970959303 |
申请日期 |
1997.10.28 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
ZAIKI, KOJI;TANAKA, TETSUYA |
分类号 |
G06F9/32;G06F9/38;(IPC1-7):G06F9/44 |
主分类号 |
G06F9/32 |
代理机构 |
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地址 |
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