发明名称 Semiconductor memory device having improved manner of data line connection in hierarchical data line structure
摘要 Segment data line pairs connected to a bit line pair are separated into segment data line pair for reading, and segment data line pair for writing. Global data line pairs connected to segment data line pair are separated into global data line pair for reading and global data line pair for writing. Connection between bit line pair and segment data line pair for reading is provided through a first read amplifier, while segment data line pair for reading is connected to global data line pair for reading through a second read amplifier. The first read amplifier includes two MOS transistors connected in series between one of the segment data line pair for reading and the ground power supply, and two MOS transistors connected in series between the other one of the segment data line pair for reading and the ground power supply. The second read amplifier includes two MOS transistors connected in series between one of the global data line pair for writing and the ground power supply, and two MOS transistors connected in series between the other one of the global data line pair for writing and the ground power supply.
申请公布号 US6118715(A) 申请公布日期 2000.09.12
申请号 US19990327418 申请日期 1999.06.08
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 ARIMOTO, KAZUTAMI
分类号 G11C11/401;G11C7/10;G11C7/18;G11C11/409;G11C11/4096;G11C11/4097;(IPC1-7):G11C7/00 主分类号 G11C11/401
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