发明名称 System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
摘要 A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.
申请公布号 US6119196(A) 申请公布日期 2000.09.12
申请号 US19970884764 申请日期 1997.06.30
申请人 SUN MICROSYSTEMS, INC. 发明人 MULLER, SHIMON;PHAM, BINH;BERG, CURT
分类号 G06F13/14;G06F9/52;G06F13/16;G06F13/362;G06F15/177;H04L12/56;(IPC1-7):G06F13/00 主分类号 G06F13/14
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