| 发明名称 |
Bus master transactions on a low pin count bus |
| 摘要 |
A system including a host, a peripheral controller device, and a bus master device each coupled to a bus having a plurality of general purpose signal lines for carrying time-multiplexed address, data, and control information. The bus master device communicates with the host and the peripheral controller device via the bus.
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| 申请公布号 |
US6119189(A) |
申请公布日期 |
2000.09.12 |
| 申请号 |
US19970936319 |
申请日期 |
1997.09.24 |
| 申请人 |
INTEL CORPORATION |
发明人 |
GAFKEN, ANDREW H.;BENNETT, JOSEPH A.;POISNER, DAVID I. |
| 分类号 |
G06F13/38;(IPC1-7):G06F13/00;G06F13/28 |
主分类号 |
G06F13/38 |
| 代理机构 |
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