| 摘要 |
This invention discloses a synchronous semiconductor memory device based on the DDR scheme. This device includes a memory cell array including first and second memory cell groups, first and second data lines, a data transfer circuit capable of at least respectively connecting memory cells included in the first and second memory cell groups to the first and second data line, a first output transfer circuit for transferring first output data sent to one of the first and second data lines at up-edge and down-edge of an operation clock, a second output transfer circuit for transferring second output data sent to the other of the first and second data lines at the up-edge and down-edge of the operation clock, and a data line control circuit capable of selectively connecting the first data line to one of the first and second output transfer circuits and selectively connecting the second data line to one of the first and second output transfer circuits.
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