| 摘要 |
<p>The invention relates to a transmission system for the synchronous digital hierarchy, having at least one adapter circuit for compensating phase fluctuations of an STM-N signal. The adapter circuit (8) contains a buffer memory (17, 51), a write-address generator (16, 53), a read-address generator (18, 61), a stuffing- decision circuit (24, 60) and an output circuit (19, 62) for insertion of stuffing digits for at least one container of the STM-N signal. The buffer memory is intended for feeding in data of the container and for reading out data of the container. The write-address generator is intended for forming write addresses for the data to be written in and the read-address generator is intended for forming read addresses for the data to be read out. In a first solution, the stuffing-decision circuit is used for forming a stuffing signal from the combination of difference values of the addresses of the read-and write-address generator and of low-pass-filtered values from values which contain the stuffing information of the data of the container to be written in. In a second solution, the stuffing-decision circuit is used for forming low-pass-filter difference values from the addresses of the read-and write-address generator and of a stuffing signal from the low-pass-filtered difference values. The output circuit is intended for forming negative or positive stuffing digits in the container in dependence on the stuffing signal and for forming an output signal from the data stored in at least one buffer memory. <IMAGE></p> |
