发明名称 DIGITAL PROCESSING PLL
摘要 PROBLEM TO BE SOLVED: To provide a standard signal oscillator at a low cost in a short time until it reaches synchronization while eliminating the effect of selective availability SA and requiring less maintenance for frequency stability equivalent to that of a cesium oscillator. SOLUTION: In the digital processing PLL that uses a PLL control section 3 comparing the output signal from a voltage controlled oscillator VCO with a reference input signal from a GPS so as to make both phases coincident with each other and to control the VCO and uses a complete integral type loop filter 16 so as to eliminate the effect of selective availability, the PLL control section 3 is provided with a synchronization discrimination processing section 19 that uses a result of detection of the change in the phase difference passing through a first peak after start of control by a change in a VCO control signal and discriminates a frequency deviation passing through zero according to the result of detection, and with a delay circuit 20 that delays the VCO control signal received when the frequency deviation passes through zero and outputs the delayed signal when the synchronization discrimination processing section 19 discriminates that the frequency deviation passes through zero.
申请公布号 JP2000244312(A) 申请公布日期 2000.09.08
申请号 JP19990039152 申请日期 1999.02.17
申请人 TOYO COMMUN EQUIP CO LTD 发明人 UMEDA TAKASHI
分类号 H03L7/095;G01S19/14;H03L7/08;H03L7/093;H03L7/107;H04L7/033 主分类号 H03L7/095
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