| 摘要 |
<p>An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadrature output of a receiver, which have been oversampled by a predetermined factor with respect to the data rate. The demodulator circuit differentiates the in-phase and the quadrature input signal by computing the difference between the current signal value and the signal value delayed by one clock period. The differentiated values of the in-phase and the quadrature signals may be changed based on the sign of the quadrature and the in-phase signals respectively to produce modified values of the differentiated in-phase and quadrature signals. Processing of the modified differentiated in-phase and quadrature values to produce an output wherein the sensitivity to noise is reduced by discarding the smaller of the modified differentiated in-phase or quadrature signal. The resulting output signal is filtered and passed through a comparator to produce a digital waveform.</p> |
