| 摘要 |
A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal ( phi CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal ( phi CH) and the error feedback signal (18) is produced by the second adder (16) and delayed by a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal ( phi CH) is spread over a broad frequency spectrum between DC and FS/2. The chopping signals are applied to corresponding chopper switches and used to reduce sensitivity of the delta-sigma modulator.
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