| 摘要 |
PROBLEM TO BE SOLVED: To optimize clock skew, to prevent malfunctions and to improve a wiring property. SOLUTION: This method is provided with a process for forming three clock signal input terminals 14-16 in a hierarchy 11, forming four clock signal input terminals 17-20 in a hierarch 12 and forming one clock signal input terminal 21 in the hierarchy 13, a process for constructing the intra-hierarchy clock line tree of the same structure connected to the clock signal input terminals 14-21 inside the hierarchies 11-13 and a process for constructing a top clock line tree 23 connected to the clock signal input terminals 14-21 at the top part of the hierarchy. The clock signal input terminals 14-21 are decided by the scale of the hierarchies 11-13 and the number of flip-flops and latches, etc., inside the hierarchies 11-13. The structure of the intra-hierarchy clock line tree to the terminals 14-21 for clock input is the same.
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