| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock changeover adjustment circuit that suppresses phase fluctuation in a selected clock signal so as to allow a PLL circuit to stably follow the phase of the selected clock signal. SOLUTION: One of the clock input systems of this circuit is provided with an inverting circuit 17 that inverts a 1/2 frequency clock signal 16 resulting from applying 1/2 frequency division to a clock signal 1 by a frequency divider 11 to provide an output of a 1/2 frequency inverted clock signal 16', a selector 12 that selects either of the signals 16, 16' and outputs the selected signal according to a prescribed switch control signal 18, and a phase difference detecting changeover control circuit consisting of a phase comparator 13, a CR integration device 14, and a comparator 15 that detects the phase difference between a selected clock signal 5 selected at present by a clock signal selection circuit 40 and the signal 16 outputted from the selector 12 in a usual state, outputs a signal 18 when the phase difference is ±90 degrees or over to allow the selector 12 to output the signal 16' or to output the signal 16 when the phase difference is ±90 degrees or below for the changeover control. |
