发明名称 SIGNAL PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To simplify access control to a memory required for error correction processing. SOLUTION: A 1st memory 2 has a capacity to store compressed picture data for 3 frames F0, F1, F2. As to a frame with an error detected therefrom, sync block data at the same image position of one preceding frame are outputted as a substitute. However, in the case that an error is detected consecutively over two frames, sync block data of the frames with the error detected therefrom are outputted as they are, and the data are replaced in the memory after expansion processing.
申请公布号 JP2000244911(A) 申请公布日期 2000.09.08
申请号 JP19990038941 申请日期 1999.02.17
申请人 VICTOR CO OF JAPAN LTD 发明人 YAMADA YASUAKI
分类号 H04N5/7826;H04N5/782;H04N5/92;H04N7/24;H04N19/00;H04N19/102;H04N19/132;H04N19/166;H04N19/172;H04N19/423;H04N19/426;H04N19/44;H04N19/65;H04N19/89 主分类号 H04N5/7826
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