发明名称 |
CLOCK ADJUSTING DEVICE IN DATA REPRODUCING SYSTEM |
摘要 |
PROBLEM TO BE SOLVED: To guarantee the sampling of a reproduced signal from a recording medium in an appropriate phase by obtaining a sampling value used for the reproduction of recorded data conforming to viterbi decoding algorithm, detecting a synchronizing point of a reproduced signal, and calculating a difference value between a level of a synchronizing point of a reproduced signal decided by a partial response characteristic and a sampling value. SOLUTION: A branch metric calculation unit BM 101 calculates a branch metric value corresponding to difference between an expected value being obtainable in a reproduced signal depending on a partial response characteristic and a sampling value. An ACS unit 102 adds a branch metric value and a path metric value one clock before being stored in a path metric memory PMM 103, compares values after addition two by two, and selects a smaller value. The almost surest data can be detected by shifting successively to data corresponding to a path in which a path metric value is always is made the minimum.
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申请公布号 |
JP2000243041(A) |
申请公布日期 |
2000.09.08 |
申请号 |
JP19990039113 |
申请日期 |
1999.02.17 |
申请人 |
FUJITSU LTD;FUJITSU PERIPHERALS LTD |
发明人 |
HAMADA KENICHI;FURUTA SATOSHI;TAGUCHI MASAKAZU;FUJIWARA TORU |
分类号 |
G11B20/14;G11B5/09;G11B7/00;G11B7/005;G11B11/10;G11B20/10;(IPC1-7):G11B20/14 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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