| 摘要 |
PROBLEM TO BE SOLVED: To prevent degradation of video quality after A/D conversion. SOLUTION: A sampling clock CLK synchronized with variable phase synchronizing signals CHSYNC is generated by using a PLL circuit 1, a clock 1/2CLK is generated by frequency dividing the sampling clock CLK by 2 and the clock 1/2CLK is latched by delay edge signals S2 for which the edge of the front side of video signals VIDEO is delayed for the 1/2 cycle of the sampling clock CLK. The latched judgment signals S3 are integrated, synchronizing signals HSYNC from the outside are sampled corresponding to the level of the integrated judgment signals S4 and the variable phase synchronizing signals CHSYNC are generated.
|
