| 摘要 |
PROBLEM TO BE SOLVED: To reduce the transient time until a stable output clock is obtained. SOLUTION: In this clock generating circuit receiving a reset signal PLL- RST, a computing element 12 measures the period of the input clock IN and calculates a count for synchronization between a delay clock DL-PUT and an input clock IN on the basis of the measured period and sets the count to a counter 13. Subsequently, the counter 13 changes its count stepwise on the basis of an output signal from a phase comparator 18. After the computing element 12 sets the count of the counter 13, a computing element 30 calculates a count for synchronization between an output clock PLL-OUT and the input clock IN and sets the count to a counter 31. The counter 31 stepwise changes its count on the basis of an output signal from a phase comparator 35 so long as two phases compared by the phase comparator 18 are coincident. |
