| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce parasitic capacitance by forming a conductive layer for grounding with a copper foil pattern formed nearly over the entire surface of a substrate on and under an intermediate conductive layer formed with a conductive channel for high frequency signal lines. SOLUTION: An inner layer 8116 is interposed between a conductive layer 8106 in the most upper layer and a conductive layer 8111 in the lowest layer of a circuit board 81. The inner layer 8116 consists of an intermediate conductive layer 8108 formed with a conductive channel 8113 for high frequency signal lines and conductive layers 8107, 8109 for grounding respectively stacked on and under the intermediate conductive layer 8108. Part of these conductive layers 8107, 8109 for grounding which is opposite to the conductive channel 8113 has a copper foil non-formed region where a copper foil 101a, 101b is not formed. Consequently, the parasitic capacitance can be reduced while reinforcing grounding to some degree.</p> |
