Controlling memory access with CPU in computer system involves CPU outputting cache read hit or miss indication signal after delay following last request, performing re-write if a hit

摘要

The method involves the CPU (110) outputting several requests at each time at which it wishes to read data from a memory unit (130) and it can output a cache read hit or miss indication signal after a delay following the last request. If a hit is indicated a cache re-write request can be output to write the output cache data from the CPU back into the memory unit after a further delay. An Independent claim is also included for a memory access control system.