An integrated memory device or store includes write-to memory cells (MC), a first differential read-amplifier (SA;SSA) with terminals connected to a data line pair (BLL;DL) allowing relevant information to be passed over the data lines as difference signals and temporarily stored at each write-access. A switch unit (SW) connects the data lines (BLL;DL) to the first read amplifier (SA;SSA) and reverse the terminals of the data lines to the read-amplifier depending on the switching state, where the latter changes at least once during a write-access so that the write-in information from the first amplifier (SA;SSA) is initially non-inverted and then inverted in the relevant memory cell (MC).
