发明名称 |
Timing circuit utilizing a clock tree as a delay device |
摘要 |
A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.
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申请公布号 |
US6114877(A) |
申请公布日期 |
2000.09.05 |
申请号 |
US19980090678 |
申请日期 |
1998.06.03 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
BROWN, C. ALLEN;SMITLENER, DAMIR |
分类号 |
H03K5/13;G06F1/10;H03H7/30;(IPC1-7):G03B13/18 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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