Device and method for multi-level charge/storage and reading out

摘要

PCT No. PCT/EP97/00561 Sec. 371 Date Dec. 14, 1998 Sec. 102(e) Date Dec. 14, 1998 PCT Filed Feb. 7, 1997 PCT Pub. No. WO97/48099 PCT Pub. Date Dec. 18, 1997The present invention discloses a memory device having memory cells capable of storing three or more charge leves in said memory cell. The cells can be programmed according to a method including a single pulse charge level injection mechanism in said cells. The method does not require a program verify scheme, permits increased speed during programming, and reduces the area necessary for storing one bit of information. The memory device of the present invention further includes information write or storage or programmation means, information erase means and information read-out means. Another object of the present invention is to provide a method and a circuit that implements said method for determining the charge level of a memory cell having t possible levels (t being larger than or equal to three). The circuit measures the similarity of the memory cell drain current with the drain current of each of n references, determines the one reference which is the most similar to the memory cell and thereby identifies the charge level of said memory cell.