Differentiating circuit and clock generator circuit using the differentiating circuit

摘要

A differentiating circuit and a clock generating circuit that do not include unwanted frequency components in a differentiated signal. An inverted signal of an NRZ (Non Return Zero) data signal is delayed by a fixed time in a delay circuit and added to a non inverted signal to generate a differentiated signal. A clock signal is generated by driving a resonator using a rectified signal produced by full wave rectifying the differentiated signal. At this time, resonant components arising due to impedance mismatching are removed by providing a LPF.