| 摘要 |
A network line equalizer is provided in combination with a compensation circuit. The network line equalizer includes first and second nodes, first and second current sources respectively connected to the first and second nodes, first and second transistors respectively connected also to the first and second nodes with a gate of the first transistor receiving a first signal of a differential pair of transmitted signals and a gate of the second transistor receiving a second signal of the differential pair of transmitted signals, a third transistor connected between the first and second nodes, and a control line connected to a gate of the third transistor. The compensation circuit includes third and fourth nodes corresponding to said first and second nodes, third and fourth current sources corresponding to the first and second current sources and respectively connected to the third and fourth nodes, fourth and fifth transistors respectively connected also to the third and fourth nodes and corresponding to the first and second transistors with a gate of the fourth transistor receiving the first signal of the differential pair of transmitted signals and a gate of the fifth transistor receiving the second signal of the differential pair of transmitted signals, a sixth transistor corresponding to said third transistor and connected between the third and fourth nodes with the control line connected also to a gate of the sixth transistor, and an output circuit configured to control the voltage on the control line. The output circuit has a current inducing circuit providing a current to a node of the control line where it is compared with a reference current. Changes in transconductance of any of the fourth through sixth transistors matching changes in transconductance of any of the first through third transistors and changing the current provided by the current inducing circuit and the voltage on the control line.
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