Surface protective layer for improved silicide formation

摘要

Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32). The semiconductor layer (12) may then be thermally treated to activate the dopants. The protective layer (50) may thereafter be removed and a metal layer (60) deposited outwardly of the semiconductor layer (12) and the gate body (14). A silicide layer (70) may be formed by interacting the metal layer (60) with the outer surface (16) of the semiconductor layer (12) and with the outer surface (22) of the gate body (14).