| 摘要 |
A semiconductor memory circuit includes a memory cell subarray, a subarray driver and a cell drain potential generator. The memory cell subarray includes word lines, memory cell transistors and a cell drain line selection transistor. Each of the memory cell transistors has a gate connected to one of the word lines, a drain and a source. The cell drain line selection transistor has a first terminal connected to the drains of the memory cell transistors, a second terminal and a gate. The semiconductor memory circuit further has a subarray driver connected to the gate of the cell drain line selection transistor for applying a predetermined potential to the cell drain line selection transistor in response to a write control signal and an address signal, and a cell drain potential generator connected to the second terminal of the cell drain line selection transistor for providing a cell drain potential to the second terminal of the cell drain line selection transistor in response to the write control signal. The cell drain potential generator has a delay circuit for slowly rising the cell drain potential.
|
