| 摘要 |
Disclosed is a low power scan flop cell design for enabling low power scan mode testing and reduced heat dissipation. The low power scan flop therefore enables "at speed" testing in scan mode, which enables comprehensive testing of high speed timing faults. The scan flop cell embodies a scan cell that has inputs that include a data input pin, a scan input (SI) pin, a scan enable (SE) input, and a clock input. The scan cell has outputs that include a Q' output and an NQ' output. The scan flop cell further includes a first logic gate having a Q output, a first input pin that is connected to the Q' output of the scan cell, and a second input pin. The scan flop also includes a second logic gate having an NQ output, a first input pin that is connected to the NQ' output of the scan cell, and a second input pin. An electrical interconnection is formed between the scan enable input of the scan cell and the second input pin of both the first logic gate and the second logic gate. A scan output (SO) pin is then connected to the Q' output that is coupled to the first input pin of the first logic gate. A scan chain including a plurality of scan flop cells can therefore be constructed, wherein the scan output (SO) of one scan flop cell leads to the scan input (SI) of the next cell. This construction therefore keeps both the Q output and the NQ output completely quite during scan mode testing, which prevents the switching of logic not in the scan chain.
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