| 摘要 |
PURPOSE: An apparatus and a method for multiplying and dividing operands by each other are provided to multiply and divide one operand by the other operand efficiently at high speed, by using a value '2N', where the N is represented as a two's complement. CONSTITUTION: A logic circuit(100) includes an inverter(102), an increment part(104), a multiplexor(106), a range detector(108) and a m-bit calculation left/right shifter(110). The inverter(102) generates the two's complement of an operand(A) with m bits. The increment part(104) is implemented by a carry look-ahead adder. The multiplexor(106) receives the N and the complement of the N plus '1', which is applied from the increment part(104), at its operand input terminals, and gets a sign bit of the N at its input selection terminal. The range detector(108) receives an absolute value of the N from the multiplexor(106). The shifter(110) includes a shift counter of (m-1) bits.
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