| 摘要 |
PURPOSE: An apparatus and a method for interfacing between a processor and a serial input/output controller, are provided to reduce a wait time in the processor in order to improve processor performance, by buffering the data output from the processor in a FIFO register regardless of data transmission speed in the controller, and allowing the controller to read the data according to the transmission speed. CONSTITUTION: A data storing status in a transmission data register and a FIFO register, installed between the processor and the controller, is searched, and thereby it is determined whether the data is stored in the FIFO register(ST1). If the data is stored in the FIFO register, it is further determined whether the data is stored in the transmission data register(ST2). The data is read from the FIFO register, and then written in the transmission data register, in case that the data is stored in the FIFO register but not in the transmission data register(ST3).
|
