I/O TOGGLE TEST METHOD USING JTAG

摘要

PURPOSE: Provided A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. CONSTITUTION: The test pattern of alternating data bits is then latched to the JTAG data latch register(220) and driven onto the output pins of the IC chip. The test pattern is then shifted by one bit within the IC's JTAG shift register(205) and parallel loaded into the JTAG latch register(220) on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip. The process is then repeated once more to provide an alternating transition for each of the output pins on the IC chip.