| 摘要 |
<p>A semi-hierarchical FPGA having a top level, a middle level and a low level. The top level having a plurality of first tiles (12), each of the plurality of first tiles having a freeway routing channel (16), and a plurality of first switch matrices (18) disposed at each corner of each of the first tiles and coupled to said freeway routing channels. The middle level having a plurality of second tiles (26), each of the plurality of second tiles having an associated horizontal and vertical expressway routing channels (M1, M2, M3). Each horizontal/vertical expressway routing channel having a tab (30) for coupling the horizontal/vertical expressway routing channel to the freeway routing channel and for coupling the horizontal/vertical expressway routing channel to the adjacent horizontal/vertical expressway routing channel. The low level (22) having a block (20), the block coupled by block connectors, and the expressway routing channels to other block connectors by a switching matrix.</p> |
