| 摘要 |
<p>An integrated circuit (10) includes a reconfigurable FIR filter (14) which has an input port for receiving digital input signals and an output coupled to a coherent signal processor and coherent memory (26). The FIR filter (14) programmably provides filtered signals to the coherent signal processor for storage in the coherent memory (26). The integrated circuit (10) further includes a sequential weight processor (30) having an input coupled to an output of the coherent memory (26). The sequential weight processor (30) includes a weight memory (36) and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit (10) is programmable into one of the plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.</p> |
