发明名称 |
DEVICE AND METHOD FOR DETECTING DELAY TROUBLE FOR PHASE LOCK LOOP CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a device and a method for detecting a delay trouble of a phase lock loop circuit. SOLUTION: A frequency impulse is impressed as a reference clock signal to an examined phase lock loop circuit 52, and a wave form of a signal output from the circuit 52 is converted into an analytical signal to estimate an instantaneous phase thereof. A linear phase is estimated based on the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to find a variation term of the instantaneous phase. A delay time is measured based on the term of the instantaneous phase. A time interval when the phase lock loop circuit 52 stays in an oscillation frequency condition is compared with a time interval when the loop 52 in the absence of a delay trouble stays in an oscillation frequency condition to detect the delay trouble. |
申请公布号 |
JP2000235063(A) |
申请公布日期 |
2000.08.29 |
申请号 |
JP20000038415 |
申请日期 |
2000.02.16 |
申请人 |
ADVANTEST CORP;MANI SOOMA |
发明人 |
YAMAGUCHI TAKAHIRO;MANI SOOMA;ISHIDA MASAHIRO |
分类号 |
G01R31/316;G01R25/00;G01R31/28;G01R31/30;H03L7/08 |
主分类号 |
G01R31/316 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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