| 摘要 |
PROBLEM TO BE SOLVED: To prevent wasteful power consumption and reduction of a bandwidth due to excessive refreshes by allowing this controller to have a refresh counter counting a cycle shorter than a refresh cycle which is stipulated in a DRAM and an address storage circuit storing addresses accessed in a fixed time and performing refreshes while excluding these addresses. SOLUTION: When data access is not performed, a timing control circuit 2 performs collective refreshes in the proportion of one time to two times of a timing signal which is to be outputted by a refresh counter 4 and whose cycle is 1/2 of a refresh cycle (tREF) which is stipulated in the DRAM. When data access is performed during tREF/2 just before the collective refreshes are to be performed, a Row address storage circuit 5 stores these Row addresses. The timing control circuit 2 performs refreshes by excluding refreshes of these Row addresses at the time of performing the collective refreshes.
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