| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory structure having a constitution of a memory cell array which can process many input/output data simultaneously in parallel and a redundant relieving circuit which can perform efficiently redundant relieving for the above. SOLUTION: A memory cell array 50 is provided with a regular memory cell array divided into plural memory mats 55, a row redundant circuit 70, and a column redundant circuit 80. A data line is provided independently for each of the regular memory cell array, the row redundant circuit 70, and the column redundant circuit 80. Each data input/output line is connected selectively to a global data bus GDB by a data line shift circuit 75. When an address signal coincides with a defective address, a redundant control circuit 60 generates a shift setting signal corresponding to a defective address, and a connection mode in the data shift circuit 75 is set.
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