Reduced cell voltage for memory device

摘要

A memory cell stores a logical "1" at a reduced voltage of VCC/2 with a cell-plate voltage of VCC/4. A pair of complementary digit lines are initially biased to VCC/2. Because the digit lines are biased to VCC/2 and a "1" is stored as VCC/2, no voltage delta appears on the digit line when the access transistor is turned on. A sense amplifier is biased to favor a logical "1" if there is no voltage differential between the digit lines in order for the data sense amplifier to correctly interpret having no voltage delta as a logical "1". The row address is used to determine which digit line has the cell charge and which digit line is the reference. Using this approach, the gate voltages of the access device and of the isolation device do not have to be higher than VCC. The use of lower cell voltage produces immediate gains in static refresh times due to the reduced leakage currents.