发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE |
摘要 |
PROBLEM TO BE SOLVED: To provide a highly reliable DRAM by obtaining a desired threshold voltage in a memory cell and at the same time improving refresh characteristics. SOLUTION: A threshold voltage of 1.1 V of a memory cell selecting MISFET (Qs) is obtained by forming a p-type semiconductor region 27 and n--type semiconductor regions 8a, 8b whose impurity concentration is relatively high in a p-type well 4 on a data line side of the memory cell selecting MISFET (Qs). Junction field strength near the end part at an information storing capacity element side of a gate electrode 7a is reduced, by not forming the p-type semiconductor region 27 in the p-type well 4 at an information storing capacity element side but by forming the n--type semiconductor region 8b whose impurity concentration is relatively low. |
申请公布号 |
JP2000236074(A) |
申请公布日期 |
2000.08.29 |
申请号 |
JP19990309114 |
申请日期 |
1999.10.29 |
申请人 |
HITACHI LTD |
发明人 |
OYU SHIZUNORI;OGISHIMA JUNJI;TSUCHIYA OSAMU;TADAKI YOSHITAKA;WATABE KOZO;UCHIYAMA HIROYUKI;IKEDA YOSHIHIRO;OKAZAKI TSUTOMU;ASAKURA HISAO;KAWAKITA KEIZO;SHIGENIWA MASAHIRO;KUBOTA KATSUHIKO;KUJIRAI YUTAKA;KAJITANI KAZUHIKO;NAGASHIMA YASUSHI;NAKAMURA MASAYUKI |
分类号 |
H01L27/108;H01L21/8242 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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