DYNAMIC LOGIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To obtain a low voltage bus signalling architecture by providing a storage circuit which stores data after it is placed in a set state, an output circuit which connects stored data to an output by responding to an output strobe pulse and a reset circuit resetting the storage circuit by responding to the falling edge of the output strobe pulse. SOLUTION: This low voltage bus signalling architecture 20 has a driver 200 and a storage part 210. The driver 200 is an n-channel MOSFET inverter and inputs an input logic signal being on a line 203. The storage part 210 has a latch 250, an output circuit 260 and a reset circuit 270. The output circuit 260 connects stored data to an output DQ by responding to an output strobe pulse PNTo1. The reset circuit 270 precharges the storage part 210 via a first transistor 240 by responding to the falling edge of the pulse PNTo1.