| 摘要 |
The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from the at least a command decoder, wherein the at least a multi-bit pre-fetch address generator circuit is connected to the at least a follower circuit element in parallel to the at least a command decoder, so that the at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of the command signal, whereby the at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of the command signal from the at least a command decoder to the at least a follower circuit element.
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