发明名称 METHOD FOR STRUCTURING LOGICAL CONFIGURATION USING ELECTRICALLY RECONFIGURABLE GATE ARRAY
摘要 PROBLEM TO BE SOLVED: To actualize the method for structuring a logical configuration by using the electrically reconfigurable gate array. SOLUTION: Electrically reconfigurable gate array(ERCGA) logic chips are connected to one another via reconfigurable interconnections. The electrical representation of a large-scale digital network is so converted as to adopt a hardware style, which operates actually and temporarily on the interconnected chips. The digital network actualized on the interconnected chips can be changed any time through reconfigured connections. Consequently, a system is adapted to various purposes which include simulation, prototyping, execution, and computation. The reconfigurable interconnections are configured by the ERCGA chips dedicated to an interconnected function. Each interconnected ERCGA is not connected to all the interconnected chips but is connected to at least one pin.
申请公布号 JP2000236249(A) 申请公布日期 2000.08.29
申请号 JP19990336488 申请日期 1999.11.26
申请人 QUICKTURN DESIGN SYST INC 发明人 BUTTS MICHAEL R;BATCHELLER JON A
分类号 G01R31/28;G06F11/22;G06F11/25;G06F15/78;G06F17/50;H01L21/82;H03K19/173;H03K19/177 主分类号 G01R31/28
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