SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To enable reducing a chip area by providing one line of a main bit line with respect to plural lines of subbit lines to which drains of memory transistors are commonly connected, connecting the plural subbit lines to switches of a first stage respectively and commonly connecting other ends of the switches and connecting other ends to main bit lines with a switch of a second stage. SOLUTION: Subbit lines formed on first wiring layers being in memory cell arraies 1-1 to 1-8 are connected to main bit lines formed in second wiring layer with Y switches 2-1 to 2-8. Main bit lines are wired so as to be passed over memory cell arraies 1-1 to 1-4, 1-5 to 1-8 to be connected to a read/write circuit 6. Power pource lines and control signal lines for respective array power sources circuits 4-1 to 4-8 are wired from array power source control circuits 5-1, 5-2 in among the main bit lines through the second wiring layer to be connected to the array power source circuits 4-1 to 4-8 of respective memory cell arraies 1-1 to 1-8.