| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein modification of a mask pattern of a wiring layer is reduced. SOLUTION: In the circuit, there are provided a logic circuit, logic circuit wiring nodes (1A, 2A, 2A, 2G, 3A) which are connected to a logic circuit and consisting of a plurality of wiring layers, a preliminary logic circuit provided for modifying logic and preliminary logic circuit wiring nodes (1B, 1D, 2C, 2E, 3B, 3C) which are connected to a preliminary logic circuit and consist of a plurality of wiring layers. The wiring nodes (1A, 2A, 2A, 2G, 3A) and the wiring nodes (1B, 1D, 2C, 3E, 3B, 3C) are made to pass through a modification object wiring layer selected from among a plurality of wiring layers. It is desirable that a preliminary logic circuit be connected to a power supply wiring 2D or a ground wiring 2F.
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