发明名称 |
Line decoder for a low supply voltage memory device |
摘要 |
A decoder comprises a first line placed at a first reference potential (VCC); a second line placed at a second reference potential switchable between the first reference potential and at least one programming potential higher than the first reference potential; a voltage elevator circuit connected to the second line, receiving a control signal and generating at an output a third reference potential switchable, on the basis of the control signal, between the first reference potential, the programming potential and a boosted potential which is between the first reference potential and the reference potential; a third line connected to the output of the voltage elevator circuit; an input circuit connected to the first line and receiving a predecoding signal, an output biasing circuit connected to said third line and generating a biasing signal for one line of the memory device; and switch circuit located between the input circuit and the biasing circuit, receiving a driving signal for selectively breaking the electrical connection between the input circuit and the biasing circuit on the basis of the driving signal.
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申请公布号 |
US6111809(A) |
申请公布日期 |
2000.08.29 |
申请号 |
US19990324087 |
申请日期 |
1999.06.01 |
申请人 |
STMICROELECTRONIS, S.R.L. |
发明人 |
MICHELONI, RINO;CAMPARDO, GIOVANNI |
分类号 |
G11C8/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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